In this fourth part of our series we will look at the heart of an electronics packaging system - the backplane (Fig. 1). This component is responsible for the data traffic and power supply to the individual function boards. The architecture of the backplane is thus determined by the type of data transmission required (parallel or serial) and the bus system specification, such as VMEbus, CompactPCI, MicroTCA or AdvancedTCA.

In an electronics packaging system the mechanical framework is provided by the enclosure, which thus includes the physical mounting of the boards. These must however remain electrically connected to one another. In the early days of system design, mating connectors were used for each board and the connectors linked via cables. Today this cabling is in most cases contained on a PCB. This board sits on the rear side of the board cage and the system boards are inserted directly into the appropriate connectors. The PCB thus replaces the original wiring between the boards, and has been termed the back-wiring board or wiring backplane. Data is transmitted between the boards via a data bus, and so an alternative term, 'bus motherboard', was used in some situations (for example the term 'Busplatine' is still common in German). The backplane is situated at the rear of the system, behind the boards, and forms the rear side of the system, and this explains the commonest name for the device - 'backplane'. However, by adding a rear I/O board cage, the system can be further extended rearwards, beyond the backplane. Now the 'backplane' is no longer the back of the system but is instead situated in the centre between the front and rear board cages. A further term has thus also entered usage, the midplane. But while the terms back-wiring board, bus motherboard and midplane are still occasionally used, the name 'backplane' is today by far the commonest term for all applications.

The backplane provides the electrical connections between the boards. It also fulfils other functions such as power distribution. The outputs from the PSU are fed into the backplane, from where they are connected to the relevant connector pins on the boards. To ensure a high current capacity and to minimise interference, entire copper layers are generally integrated into the backplane for the main supply voltages. In the past, the commonest voltage was 5 VDC. Since the processors and controllers normally required 3.3 V, however, a second main supply voltage of 3.3 VDC to the boards later became common. Today's boards are often supplied at 12 V and the lower voltages for the logic components derived from this on-board. A reason for this is that the supply voltages for processors and controllers have come to vary considerably, and are generally very low. In addition to its electrical functions, the backplane adds an important element of mechanical stability to the system. In almost all cases backplanes are formed out of multiple layers of copper tracks separated by insulating layers, these typically of FR4 (epoxy resin with fibreglass reinforcement mat). Today a backplane may contain from 4 to over 30 layers and thus have a thickness of between 2.4 mm and 8 mm or more. By bolting the backplane to at least every second slot, therefore, a very mechanically stable system construction is obtained.

The main task of the backplane remains the transfer of digital data. The volume of data exchanged between the boards has increased rapidly in recent years. For a long time now one data line between the communication partners has no longer been sufficient. One solution has been to connect multiple lines in parallel, thus allowing multiple bits to be transmitted simultaneously. Such a structure is known as a parallel bus. In this configuration the parallel data lines are connected to every slot in the system, so linking all communication partners into the data bus. The bus width - that is, the number of parallel lines - is normally a multiple of one byte (8 bits), e.g. 16, 32, 64 or 128 bit. In theory, the number of parallel lines can be increased without limit to enable ever greater volumes of data to be transmitted. This would however mean that the number of pins on the connectors would also have to be continually increased, and in practice this is limited by the physical size of the slot. An alternative option for increasing the volume of data sent in a given time interval might also be to increase the rate of transmission. Yet here again there are limits for a parallel bus. Firstly, sender and receiver must be synchronised using a clock signal, so that the receiver is informed of the time period during which the bits are present on the parallel lines. However, tolerances in the bus driver chips, in the PCB materials and particularly in the different boards on the bus, lead to slight variations ('skew') in the signal period of each individual line. It follows that the clock period may not be shorter than the longest potential skew time between the lines of the bus. The more parallel lines are present on the bus, the more difficult is the synchronisation. A further limiting factor on the bus speed is the response speed of the bus driver. The switching action from logic 0 to logic 1 or from 1 to 0 requires a finite time, known as the rise time. In the transition from the low state to the high state (logic 0 to logic 1) the signal is not detected as high until the rise time has elapsed. It is thus desirable for faster data transfer that this rise time be reduced to the shortest possible. This can be achieved e.g. by reducing the voltage swing from 5 V to 3.3 V. But here again there are limits; the receiver chips must still be capable of differentiating between the high and low state. One trick to improve the situation is known as low-voltage differential signalling (LVDS). This form of data transmission uses a voltage differential of only 0.3 V, while a change between low and high states is signalled by reversing the polarity of the voltage. Additionally a second line accompanies the first and carries the same signal, but inverted. The result is an effective voltage swing of 1.2 V, which today's receiver chips can detect reliably.

When using LVDS, we are no longer speaking of a parallel bus. No longer are all the slots connected via a single bus; instead, point-to-point connections are formed between each pair of boards. In order that all the boards in the system can exchange data with one another, the so-called star topology is used: each slot is connected to a special slot known as the switch slot. This switch slot contains a data switch that 'routes' the incoming data to the appropriate receiver. Where only one processor board is present in a system a further possibility is to make the processor slot the hub of the star, i.e. the point to which all the lines are connected. Here the processor board also takes on the task of data distribution. The necessary data switches are already present in today's processor chipsets, so no additional switch board is required.

In serial data transmission, further configurations (backplane topologies) are possible, rather than a single star point, a dual star configuration may be used (Fig. 2). The second star point contains a further data switch, which in most cases provides failure safety. This second, redundant switch takes over the function of the first, should this fail (redundancy operation).

It can however alternatively be used to double the data transmission rate. In AdvancedTCA the idea has been extended to a full-mesh topology. In this configuration each board is connected to each other via 4 data ports. Now the data does not have to be sent via a star point but rather is routed direct to the receiver. The price of this high performance is however a considerably larger number of lines in the backplane, more connectors per slot and a larger number of layers in the PCB. A maximum of 16 slots are possible in a full-mesh AdvancedTCA backplane. This requires 60 ports per slot, which amounts to 240 lines (connector pins). The lines and pins must additionally be shielded, which requires additional earthing pins. For synchronisation between sender and receiver, additional lines are also required for a clock signal. In smaller systems with fewer slots, the free higher ports can also be connected to the other slots. Where e.g. only 8 instead of 16 slots are present on the backplane, eight rather than four ports may be connected to all the slots. The result is known as a replicated mesh. For applications that call for the sequential operation of the individual boards, and where this sequence is always the same, a daisy-chain configuration can also be realised. In such an arrangement, all the slots are connected in series to one another.

Since in a parallel bus all communication partners are connected to the same lines (multipoint/multidrop), multiple boards may not send data at any given time. Thus while one board is sending data, the bus is blocked to all other subscribers. A system of sender priorities must be established to define how this is to occur, e.g. via the daisy chain in VME backplanes or via request/grant lines in CompactPCI. In serial data transmission this restriction no longer applies. Subscriber A can send data to B and simultaneously subscriber C can transmit to D. Under current standards, each connection has two differential pairs - one for sending data and the other for receiving. Thus data can be sent simultaneously between two boards in both directions. These two differential pairs are termed a "port" or "lane". Meanwhile, to further increase the data rate, multiple ports are connected in parallel between two subscribers. The sum of all the ports between two subscribers is known as the link. It is common practice to use 4 ports per link for backplanes. In PC applications, however, a 16-port link is already in common use between the CPU and the graphics card (PCI Express x16).

The most immediate advantage of serial data over LVDS in relation to the parallel bus is its maximum data transfer rate. For a 64-bit PCI bus this amounts to 533 MB/s (megabytes per second). In its second generation PCI Express, the serial successor to PCI bus, already offers a data transfer rate of 5 Gb/s on a single LVDS pair. Since up to 16 ports can be used in parallel, the maximum rate adds up to 80 Gb/s. These 80 Gb/s can also be both sent and received simultaneously.

To avoid reinventing the wheel for every application and to prevent the proliferation of manufacturer-specific bus systems, a system of standardising is unavoidable. Standardisation ensures that the products of different manufacturers will work smoothly together. A wide variety of products is available on the market for the various standards, and thus suitable solutions are available from different providers for the most diverse of tasks.

At present two organisations are concerned with the standardisation of bus systems in the backplane and systems sector. VITA (VMEbus International Trade Association) was formed in 1984 and consists of manufacturers active in modular electronics packaging systems. In 1984 VITA published its first bus specification, VMEbus. The VMEbus is a parallel 16 or 32-bit bus designed as a multi-user bus for process control. In 1994 the VME64 standard was issued. In the ensuing years a number of sub-specifications appeared, such as the VME64x standard, which allowed an increase in the data rate through additional GND pins and which also made additional rear I/O pins available. Since the beginning of the millennium VITA has developed new specifications for serial transport mechanisms on the backplane. VITA 31 implemented gigabit data transfer on the P0 connector, VITA 41 (VXS) defines a new connector that offers serial data transfer at up to 10 Gb/s and VITA 46 (VPX) applies this high-speed connector to the entire slot and thus enables a wide range of backplane topologies. It allows both parallel transfers using VME or PCI and serial protocols such as PCI Express, 10 GbE (Gigabit Ethernet) and Serial Rapid I/O. In addition, daisy-chain, star, dual star and mesh topologies may be realised.

The second organisation is PICMG (PCI Industrial Computer Manufacturers Group), founded in 1994. The original mission of this body was to introduce the PCI standard, defined by the PCI Special Interest Group for the computer market, to the 19" form factor and to adapt it to the harsher areas of application in industry. The result of this was the PICMG 2.0 CompactPCI specification. This specification was periodically revised in the following years, and the current revision is version 3.0. A number of sub-specifications were also developed, some of which define additional buses, e.g. PICMG 2.5 (Computer Telephony Specification) and 2.16 (Packet Switching Backplane), and also expansions such as 2.11 (CompactPCI Power Interface Specification) and PICMG 2.9 (System Management Bus). A new standard for the telecoms market was issued in 2002, the PICMG 3.0, AdvancedTCA. Subsequently the AdvancedMC and MicroTCA specifications appeared, which were likewise intended primarily for the telecoms market. However, with the Rugged MicroTCA specifications MicroTCA.1 to 3 now being developed, a sound basis is also being created for MicroTCA in industrial and military environments. Two additional working groups are defining AdvancedTCA for industrial and physical applications. PICMG is currently working on a solution for the CompactPCI bus, which is still based on parallel data transfer. CompactPCI Plus, so called because this specification is close to that of CompactPCI, makes the new serial interfaces such as PCIe, SATA, USB and Ethernet available for industrial uses.

Constantly increasing complexity and rising data rates mean increasing demands on development, layout, validation, simulation and testing. While just a few years ago high-speed backplanes were still a rare exception, the arrival of PCI Express, Gigabit Ethernet and Serial Rapid I/O has made them the everyday concern of all backplane developers. As a consequence, new requirements are also being made on manufacturing and particularly on design validation.

Previously, in both proprietary designs and 'standard' backplanes such as VMEbus or (C)PCI, a parallel bus with clock speeds of up to a few tens of MHz was often the state of the art for communications technology. Protocols were sufficiently robust to withstand crosstalk and transit-time effects. More critical were groundshift effects and simultaneous switching noise. As for validation, it was sufficient to take an impedance profile and where necessary to determine the crosstalk on clock or strobe lines. Crosstalk between data lines was practically never a problem.

The changeover from parallel buses to packet-orientated serial data transport mechanisms does not alter the laws of physics, but it brings new design rules. With clock speeds more than 100 times faster, they have had to be completely rewritten. As the clock frequency rises, the wavelength of the signal components is reduced. While previously the longest lines in the backplane were short relative to the signal wavelength, today the vias (through-contacts between layers on the PCB) approach a quarter of the wavelength, at which point their design becomes critical. 3D simulations and a manufacturing process that can guarantee high-precision implementation of the design parameters have become indispensable. In addition to the impedance profile, of particular importance to validation are measurements in the frequency domain and statistical calculations in order to keep criteria such as the bit error rate to acceptable levels. Simulations and measurements (Fig. 3) naturally also aid in the optimising of the cost-to-performance relationship by helping to reduce the number of layers.

Most important for the developers and designers in order to realise backplanes for the new technologies is the necessary know-how and experience, supported by realistic simulations. A wide spectrum of available standard backplanes for a diversity of topologies and specifications is also important and forms the basis for custom modifications. Custom backplane configurations are forming an increasing percentage of designs overall. The broad spectrum of possible configurations for systems with serial data transfer such as CompactPCI Plus, MicroTCA and AdvancedTCA will cause this trend to increase still further. Custom configurations also showcase the advantages of a complete system provider: all components, including the backplane, are intelligently matched to the system. The close collaboration between mechanical and electronic development teams ensure the best possible matching of the components to one another.

The high demands on development and design naturally also extend to the manufacturing process. Here the central issues are manufacturing quality, precision and cost. As concerns backplanes, some projects have highly varied batch sizes, beginning with 1 to 10 prototypes, that may subsequently lead to the serial production of several thousand. For the backplane manufacturer, therefore, a high level of flexibility is vital. The production line should be set up to allow short retooling times while also providing the necessary precision and quality. An example of a flexible production tool is the solder paste printer (Fig. 4), which is simply 'fed' with CAD files and can thus quickly change over from one backplane to another.

This printer also avoids the usual need for screens, which thus saves both time for prototype production and the extra cost of the screens. In SMD soldering, the highest quality is obtained by the "steam phase", which offers a more homogenous temperature distribution than traditional reflow and wave soldering systems, and the temperatures are also substantially lower. Quality assurance is another important aspect that should not be neglected. Backplanes are often used for periods of well over ten years, and it is thus important that a high standard of quality be maintained in terms of production facilities, qualified personnel and the appropriate testing equipment. An example of the latter is AOI (automatic optical inspection), which checks the backplane for faults such as missing components, component polarity, short circuits and dry or poor soldered joints. Safety tests such as high-voltage insulation tests and earthing tests are also important, as are function tests.